High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US6992925B2 · kind B2 · utility
239Cited by
97References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2004 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.