Method circuit and system for read error detection in a non-volatile memory array
US6992932B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Feb 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method, circuit and system for determining a reference voltage to be used in reading cells programmed to a given program state. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in a NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read and the number of cells found at a given state associated with the array may be compared to one or more check sum values obtained during programming of the at least a subset of cells. A Read Verify threshold reference voltage associated with the given program state or associated with an adjacent state may be adjusted based on the result of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.