Column redundancy for digital multilevel nonvolatile memory
US6992937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Oct 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.