Delay locked loop implementation in a synchronous dynamic random access memory
US6992950B2 · kind B2 · utility
71Cited by
57References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 21, 2003 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.