Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types
US6994939B1 · kind B1 · utility
169Cited by
10References
28Claims
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Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Apr 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/32
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.