Semiconductor package including passive elements and method of manufacture
US6995448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/927
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.