Integrated semiconductor circuit having a cell array having a multiplicity of memory cells

US6998664B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Joerg Vollrath · Richmond, US
• Stephan Schröder · Birkenfeld, DE
• Tobias Hartner · Munich, DE

Key dates

• Filing date: Feb 27, 2004
• Grant date: Feb 14, 2006
• Expiry date: Jun 8, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

An integrated semiconductor circuit includes a cell array having memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.