Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode

US6998678B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Werner · Hersbruck, DE
• Franz Hirler · Isen, DE
• Joachim Krumrey · Eisenlohrsweg, AT
• Walter Rieger · Arnoldstein, AT

Key dates

• Filing date: May 16, 2002
• Grant date: Feb 14, 2006
• Expiry date: May 16, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed by a Schottky contact between a source electrode and the semiconductor body.