Circuit and method for monitoring defects
US6998866B1 · kind B1 · utility
8Cited by
17References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2004 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Sep 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.