Method for limiting slip lines in a semiconductor substrate
US7001832B2 · kind B2 · utility
1Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 5, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | May 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for limiting slip lines in a semiconductor substrate including a support layer and a useful semiconductor layer that is transferred to the support layer. The method includes precipitating at least a portion of interstitial oxygen in the support layer by a series of heat treatments conducted after bonding of the useful semiconductor layer to the support layer. The heat treatments occur at a temperature and a time sufficient to reduce the generation of slip lines therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.