Method for package reduction in stacked chip and board assemblies
US7005316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2002 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jan 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.