Method for producing a memory cell of a memory cell field in a semiconductor memory
US7005346B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | May 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0387
Abstract
A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a technologically more reliable fashion. This is achieved by virtue of the fact that two first trenches running parallel and having a first depth are etched in the semiconductor substrate. Between the trenches is formed a web, which is connected to the semiconductor substrate at its narrow sides and which is severed at its underside and is separated from the semiconductor substrate. The suspended web is then provided with a closed dielectric. After a filling, the FET is applied and connected to the web as memory node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.