Depletion drain-extended MOS transistors and methods for making the same
US7005354B2 · kind B2 · utility
10Cited by
16References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 23, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Sep 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.