Method for fabricating semiconductor memories with charge trapping memory cells

US7005355B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Christoph Kleint · Dresden, DE
• Christoph Ludwig · Radeberg, DE
• Joachim Deppe · Dresden, DE
• Jens-Uwe Sachse · Dresden, DE

Key dates

• Filing date: Dec 12, 2003
• Grant date: Feb 28, 2006
• Expiry date: Aug 1, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.