Tri-gate devices and methods of fabrication
US7005366B2 · kind B2 · utility
86Cited by
14References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.