Semiconductor device and method
US7005717B2 · kind B2 · utility
30Cited by
566References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | May 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Circuit (10) has a dual layer gate dielectric (29) formed over a semiconductor substrate (14). The gate dielectric includes an amorphous layer (40) and a monocrystalline layer (42). The monocrystalline layer typically has a higher dielectric constant than the amorphous layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.