Memory module having interconnected and stacked integrated circuits
US7005730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Mar 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.