Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip
US7006940B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Oct 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48139
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for testing a first integrated circuit chip which is packaged along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are shared by the first and second integrated circuit chips. The method and system include: powering down the second integrated circuit chip; tri-stating a plurality of input/output (I/O) drivers of the second integrated circuit chip so that the plurality of I/O drivers do not drive any signals onto any connections for the shared external terminals; and performing testing of the first integrated circuit chip according to one or more regular testing routines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.