Leadframe strip having enhanced testability
US7008825B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor package comprising the step of providing a leadframe strip which defines a strip plane and a multiplicity of leadframes. Each of the leadframes includes an outer frame defining a central opening and a die pad disposed within the central opening. Each leadframe further includes a plurality of leads which are attached to the outer frame and extend toward the die pad in spaced relation to each other. The outer frames are integrally connected to each other and collectively define connecting bars which extend in multiple rows and columns and define saw streets. Semiconductor dies are attached to respective ones of the die pads, with the semiconductor dies being mechanically and electrically connected to the leads of respective ones of the leadframes. Thereafter, an encapsulant material is applied to the leadframe strip to form at least one mold cap which at least partially encapsulates the leadframes, the semiconductor dies, and the conductive wires. The leadframe strip and the mold cap collectively define a package strip. Isolation cuts are formed through the package strip along at least some of the saw streets to effectively electrically isolate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.