Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts

US7008849B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Grit Schwalbe · Dresden, DE
• Kae-Horng Wang · Villach, AT
• Klaus Feldner · Dresden, DE
• Elard Stein Von Kamienski · Dresden, DE

Key dates

• Filing date: Dec 1, 2003
• Grant date: Mar 7, 2006
• Expiry date: Jan 22, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.