Memory device with an alternating Vss interconnection
US7009271B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | May 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A semiconductor memory device provides non-volatile memory with a memory array having an alternating Vss interconnection. Using the alternating Vss interconnection, a low implant dosage is added to a region proximate to the lower areas of an STI region, such as beneath the STI region, to ameliorate the problem of low Vss conductivity by providing an adequate number of multiple current paths over several Vss lines. However, non-adjacent STI regions, rather than adjacent STI region, receive the implant. Alternating Vss lines are interconnected by thus implanting under every other STI region. This alternating Vss interconnection imparts an adequately high Vss conductivity, yet without diffusion areas merging to isolate the associated memory device or contaminating the drains and maintains scalability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.