Low-k interlevel dielectric layer (ILD)
US7009280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | May 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%–10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.