Configurable address generator and circuit using same
US7010664B1 · kind B1 · utility
6Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Apr 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.