Eric R. Keller
32Patents
13h-index
29Co-inventors
81Inventor score
Filing activity: Feb 9, 2000 → Mar 4, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6487709B1 | Run-time routing for programmable logic devices | Electricity | 219 | Expired |
| US6920627B2 | Reconfiguration of a programmable logic device using internal control | Electricity | 157 | Expired |
| US6725441B1 | Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices | Physics | 130 | Expired |
| US7328335B1 | Bootable programmable logic device for internal decoding of encoded configuration data | Electricity | 74 | Expired |
| US7185309B1 | Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip | Physics | 43 | Expired |
| US7689726B1 | Bootable integrated circuit device for readback encoding of configuration data | Electricity | 39 | Active |
| US7574680B1 | Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip | Physics | 34 | Active |
| US6883147B1 | Method and system for generating a circuit design including a peripheral component connected to a bus | Physics | 32 | Expired |
| US7552042B1 | Method for message processing on a programmable logic device | Electricity | 20 | Expired |
| US7228520B1 | Method and apparatus for a programmable interface of a soft platform on a programmable logic device | Physics | 18 | Expired |
| US7653895B1 | Memory arrangement for message processing by a plurality of threads | Electricity | 16 | Active |
| US7131077B1 | Using an embedded processor to implement a finite state machine | Physics | 14 | Expired |
| US7111215B1 | Methods of reducing the susceptibility of PLD designs to single event upsets | Electricity | 14 | Expired |
| US7386826B1 | Using redundant routing to reduce susceptibility to single event upsets in PLD designs | Electricity | 13 | Expired |
| US11429407B2 | Apparatus, method, and system to dynamically deploy wireless infrastructure | Physics | 11 | Active |
| US7770179B1 | Method and apparatus for multithreading on a programmable logic device | Physics | 10 | Active |
| US7990867B1 | Pipeline for processing network packets | Electricity | 9 | Active |
| US7227378B2 | Reconfiguration of a programmable logic device using internal control | Electricity | 9 | Expired |
| US7028283B1 | Method of using a hardware library in a programmable logic device | Physics | 8 | Expired |
| US7698449B1 | Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element | Physics | 7 | Active |
| US8806032B2 | Methods and apparatus to migrate border gateway protocol sessions between routers | Electricity | 6 | Active |
| US7784014B1 | Generation of a specification of a network packet processor | Physics | 6 | Active |
| US7010664B1 | Configurable address generator and circuit using same | Physics | 6 | Expired |
| US7823162B1 | Thread circuits and a broadcast channel in programmable logic | Physics | 5 | Active |
| US8065130B1 | Method for message processing on a programmable logic device | Electricity | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.