Address sequencer within BIST (Built-in-Self-Test) system
US7010736B1 · kind B1 · utility
86Cited by
9References
28Claims
0Family size
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Key dates
| Filing date | Jul 22, 2002 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Dec 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.