Methods of forming a transistor with an integrated metal silicide gate electrode
US7012024B2 · kind B2 · utility
13Cited by
11References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2003 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Sep 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the trench and on the metal silicide. Optional trench spacers can be added to reduce the critical dimension restraints of a given fabrication process and thus form a transistor having smaller feature sizes than the critical dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.