Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts

US7015092B2 · kind B2 · utility

Assignee

• Infineon Technologies North America Corp. · US

Inventors

• Venkatachalam C. Jaiprakash · Sunnyvale, US
• Norbert Arnold · Pfalzgrafenweiler, DE

Key dates

• Filing date: Dec 18, 2003
• Grant date: Mar 21, 2006
• Expiry date: Dec 18, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

Methods and devices that provide improved isolation and alignment of gate conductors or gate contacts of vertical transistors in deep trench memory cells. A method for forming a vertical gate contact of a vertical transistor includes an oxide spacer formation process that prevents defects, such as shorts caused by voids filled with polysilicon, resulting from etching processes that are performed during fabrication of a vertical transistor, and enables formation of well-defined contact plugs for gate contacts, providing improved alignment structures.