Methods and structure for an improved floating gate memory cell
US7015098B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Aug 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory cell also includes a shallow trench isolation (STI) region having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. The memory cell further includes a second insulating layer formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region. Arrays, memory devices, and systems are further included in the scope of the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.