Dual work function semiconductor structure with borderless contact and method of fabricating the same
US7015552B2 · kind B2 · utility
3Cited by
34References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 4, 2005 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Apr 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.