Process controls for improved wafer uniformity using integrated or standalone metrology
US7018855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Dec 24, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/907
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for measuring multiple locations on a wafer for controlling a subsequent semiconductor processing step to achieve greater dimensional uniformity across that wafer. The method and apparatus maps a dimension of a feature at multiple locations to create a dimension map, transforms the dimension map into a processing parameter map, and uses the processing parameter map to tailor the subsequent processing step to that specific wafer. The wafer can also be measured after the processing to compare an actual outcome with the targeted outcome, and the difference can be used to refine the transformation from a dimension map to a processing parameter map for a subsequent wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.