Method of protecting an element of an integrated circuit against the formation of a metal silicide
US7018865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jun 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor material is protected against the formation of a metal silicide by forming a layer of a silicon/germanium alloy on the material. The material which is protected belongs to a component of an integrated circuit comprising other components that have to be subjected to a siliciding operation. The method of protection includes depositing a layer of silicon/germanium alloy on the integrated circuit. The layer of silicon/germanium alloy is then removed from the areas to be silicided. A metal is then deposited on the structure and a metal silicide is formed therefrom. The unreacted metal and the metal/silicon/germanium ternary alloy that may have formed are removed, and the layer of silicon/germanium alloy is removed so as to expose the unsilicided component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.