Non-volatile two transistor semiconductor memory cell and method for producing the same

US7018898B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Schuler · Kreßbronn, DE
• Georg Tempel · Zorneding, DE

Key dates

• Filing date: Dec 10, 2002
• Grant date: Mar 28, 2006
• Expiry date: Dec 10, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/0433
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3′) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.