Arrangement for ESD protection of an integrated circuit

US7019382B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Andrej Litwin · Stockholm, SE
• Ola Pettersson · Järfälla, SE

Key dates

• Filing date: Mar 2, 2004
• Grant date: Mar 28, 2006
• Expiry date: Mar 3, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (2), a semiconductor varistor (3) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad (2) and the input/output terminal together with the integrated circuit (1).