Device and method for compensating defect in semiconductor memory
US7020003B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for compensating a semiconductor memory defect suitable for a semiconductor memory is provided. The device comprises: a memory array, the memory array having a memory region consisting of a plurality of memory cells, the memory array being coupled to the address decoder circuit and the sensing circuit for storing data, if the memory array has a defect, the memory array is divided into a plurality of sub-memory regions, wherein one of the plurality of sub-memory regions is defectless, the memory array is replaced by the defectless sub-memory regions for storing data. A selection circuit coupled to the control unit, selects one of the memory region and the defectless sub-memory region to store data. A first input address buffer coupled to the control unit and the address decoder circuit has an address input port and an address output port. The address input port receives a most significant bit address signal, wherein if the memory array is defectless, the selection circuit outputs a selection signal to select the memory region to store data and makes the control unit control the address output port to output the most significant bit address signal to the address decoder circ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.