Methods and apparatus for laser marking of integrated circuit faults
US7020582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jun 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods are provided for marking integrated circuit defects on wafers to facilitate failure analysis. A wafer containing integrated circuits can be tested using a tester. Test data from the tester can be analyzed using integrated circuit design files to identify suspected faults. A fault location program can be used to identify the physical location of the faults. The fault location program uses information on the faults identified and CAD file information on the physical layout of the integrated circuit to map identified faults to actual physical positions. The fault location program may also generate laser control files. The laser control files can be used to control a laser system so that the laser system creates laser marks on the wafer surrounding each of the faults. The marked faults can be polished and examined under an electron microscope or analyzed using other failure analysis tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.