Blocking processing restrictions based on page indices
US7020761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.