Stack gate with tip vertical memory and method for fabricating the same

US7022573B2 · kind B2 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Ching-Nan Hsiao
• Ying-Cheng Chuang · Taoyuan, TW
• Chi-Hui Lin · Taipei, TW

Key dates

• Filing date: Jul 2, 2004
• Grant date: Apr 4, 2006
• Expiry date: Jul 29, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6894

Abstract

A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.