Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration
US7022625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2002 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Nov 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first deposited on a semiconductor substrate, allowing a subsequent thermal oxidation procedure to grow a thin silicon dioxide layer on the semiconductor substrate, underlying the porous, silicon rich silicon nitride layer. A two step anneal procedure is then employed with a first step performed in a nitrogen containing ambient to densify the porous, silicon rich silicon nitride layer, while a second step of the anneal procedure, performed in an inert ambient at a high temperature, reduces the foxed charge at the silicon dioxide-semiconductor interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.