Semiconductor package structure with reduced parasite capacitance and method of fabricating the same
US7023085B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Aug 18, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.