Method of optimizing the timing between signals
US7024326B2 · kind B2 · utility
4Cited by
1References
19Claims
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Key dates
| Filing date | Apr 30, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of optimizing the timing between signals to be latched and a respective latching clock signal is suggested wherein test timings are provided according to which a delay test value of a clock delay line (CDL) are generated. According to the delay test values a clock signal (C) and a sample signal (S) are received through said clock delay line (CDL) and through said sample signal line (SSL), respectively. Respective phase differences for the distinct delay test values are obtained. A delay value is chosen and set for operation for which the respective obtained phase difference fits best to given target timing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.