Parasitic capacitance-preventing dummy solder bump structure and method of making the same
US7026234B2 · kind B2 · utility
10Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Aug 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.