Device and method for detecting alignment of active areas and memory cell structures in DRAM devices
US7026647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Jan 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.