Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size
US7026679B2 · kind B2 · utility
3Cited by
15References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Jan 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.