Method of fabricating a flash memory cell
US7029973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Nov 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of second oxide layers on surfaces of the control gates and aside the control gates. The dielectric layer and the floating gate layer are etched by utilizing the second oxide layers as a mask to form a floating gate underneath each of the control gates. A source is formed between the floating gates. The floating gates and the substrate are oxidized to form a plurality of first oxide layers aside the floating gates and form a third oxide layer on a surface of the source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.