Layout correction algorithms for removing stress and other physical effect induced process deviation
US7032194B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.