Selective etch process for making a semiconductor device having a high-k gate dielectric
US7037845B2 · kind B2 · utility
17Cited by
26References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.