Method for fabricating semiconductor device with fine patterns
US7037850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3081
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns. The method includes the steps of: forming a hard mask insulation layer on an etch target layer; forming a hard mask sacrificial layer on the hard mask insulation layer; coating a photoresist on the hard mask insulation layer; performing selectively a photo-exposure process and a developing process to form a photoresist pattern having a first width for forming a line pattern; etching selectively the hard mask sacrificial layer by using the photoresist pattern as an etch mask to form a sacrificial hard mask having a second width; removing the photoresist pattern; etching the hard mask insulation layer by controlling excessive etching conditions with use of the sacrificial hard mask as an etch mask to form a hard mask having a third width; and etching the etch target layer by using the sacrificial hard mask and the hard mask as an etch mask to form the line pattern having a fourth width, wherein the first width is wider than the fourth width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.