Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method

US7038255B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Böttner · Munich, DE
• Stefan Drexl · Mering, DE
• Thomas Huttner · Marktoberdorf, DE
• Martin Seck · Birkenfeld, DE

Key dates

• Filing date: Jun 21, 2004
• Grant date: May 2, 2006
• Expiry date: Jun 21, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) and if the edge terminal region (120) has a part near the substrate which is arranged in the cutout (142) and a part remote from the substrate which is arranged outside the cutout (142) and overlaps the base terminal region (139).