Semiconductor device
US7038961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2004 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Apr 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.