Semiconductor device including impurity layer having a plurality of impurity peaks formed beneath the channel region
US7042051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76243
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.